This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-250516, filed Sep. 3, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor memory device. More particularly, the invention relates to the technique of screening the bit lines provided in a semiconductor memory device having a shared sense amplifier system, some of the bit lines connected to one side of a sense amplifier and conducting a leakage current and the others of the bit lines connected to the other side of the sense amplifier. The invention also relates to the technique of reducing a standby current generated from the leakage current flowing in the bit lines of such a semiconductor memory device.
In recent years, occurrence of a bit line leakage current becomes significant with an increase in the integration density of a semiconductor memory device as is represented by a leakage current occurring in a short circuit between a bit line and a word line. The short circuit between the bit line and the word line which is the main cause of the bit line leakage current causes the following problem if a dynamic RAM (DRAM) is taken as an example. That is, at the standby time, paired bit lines are kept at a preset bit line precharged potential (VBL). Generally, the precharge potential is set to half the high-level potential of the bit line. At this time, the potential of the word line is set at a low level. Therefore, if a short circuit portion occurs between the bit line and the word line, a leakage current will continuously flow from the bit line which is set at the preset precharge potential (VBL) to the word line which is set at the low level potential (for example, ground potential). As a result, the potential of the bit line which is short-circuited to the word line is lowered. The amount of a lowering in the bit line potential depends on a resistance between the short-circuited bit line and word line and the conductance of a precharge current limiting element connected to the bit line.
In this case, a special problem occurs in a case where a semiconductor memory device using a shared sense amplifier system in which the sense amplifier is commonly used for adjacent bit lines and which recently becomes dominant is used. In the semiconductor memory device using the shared sense amplifier system, a bit line disposed adjacent to and on the opposite side of a defective bit line which is short-circuited with the word line with the sense amplifier disposed therebetween is also influenced by the short circuit and the operation margin thereof is reduced, but since the amount of the reduction is small in comparison with the bit line which is short-circuited, it becomes extremely difficult to detect the bit line by effecting the screening operation. As a result, the semiconductor memory device passes a test in the wafer state, is subjected to the post process without replacing the defective bit line by a redundancy circuit and is detected defective in the product test effected after it is assembled into a package, and in the worst case, there is a possibility that it may be shipped as a product.
The product having the bit line leakage current is one of the main causes which increase the number of defective products in the market since a resistance between the bit line and the word line which are short-circuited with each other is lowered by an influence due to the deterioration with time or the like. Therefore, a method for effectively screening the bit line having the bit line leakage current is indispensable.
FIG. 1 shows the conventional semiconductor memory device and shows one example of a representative shared sense amplifier and bit line precharge/equalizing circuit. The circuit includes an N-channel sense amplifier 10, P-channel sense amplifier 11, bit line precharge/equalizing circuits 20, 21 and bit switches 40, 41.
The bit line precharge/equalizing circuit 20 is connected to paired bit lines BLL, /BLL to precharge the paired bit lines BLL, /BLL and equalize the potentials thereof so as to set the potentials thereof to a bit line precharge potential VBL. One end of the current path of a cell transistor TN50 is connected to the bit line BLL and the gate thereof is connected to a word line WLL. A cell capacitor C10 is connected between the other end of the current path of the cell transistor TN50 and the ground node. The cell transistor TN50 and the cell capacitor C10 are combined to form a memory cell.
The bit line precharge/equalizing circuit 21 is connected to paired bit lines BLR, /BLR to precharge the paired bit lines BLR, /BLR and equalize the potentials thereof so as to set the potentials thereof to the bit line precharge potential VBL. One end of the current path of a cell transistor TN51 is connected to the bit line BLR and the gate thereof is connected to a word line WLR1. A cell capacitor C11 is connected between the other end of the current path of the cell transistor TN51 and the ground node. The cell transistor TN51 and the cell capacitor C11 are combined to form a memory cell. Further, one end of the current path of a cell transistor TN52 is connected to the bit line /BLR and the gate thereof is connected to a word line WLR2. A cell capacitor C12 is connected between the other end of the current path of the cell transistor TN52 and the ground node. The cell transistor TN52 and the cell capacitor C12 are combined to form a memory cell.
The N-channel sense amplifier 10 and P-channel sense amplifier 11 are arranged adjacent to each other. The bit switch 40 is disposed between the bit line precharge/equalizing circuit 20 and the sense amplifiers 10, 11 and the bit switch 41 is disposed between the bit line precharge/equalizing circuit 21 and the sense amplifiers 10, 11. Further, the current paths of column select transistors TN30, TN31 are connected between the sense amplifiers 10, 11 and paired data lines DL, /DL. A column select signal CSL is supplied to the gates of the column select transistors TN30, TN31.
The N-channel sense amplifier 10 is constructed by N-channel MOS transistors TN11, TN12 and the operation thereof is controlled by an N-channel sense amplifier control signal xcfx86SN. The P-channel sense amplifier 11 is constructed by P-channel MOS transistors TP11, TP12 and the operation thereof is controlled by a P-channel sense amplifier control signal xcfx86SP.
The bit line precharge/equalizing circuit 20 is constructed by N-channel MOS transistors TN20 to TN22 and the bit line precharge/equalizing circuit 21 is constructed by N-channel MOS transistors TN23 to TN25. A precharge/equalizing circuit control signal xcfx86EQL is supplied to the gates of the MOS transistors TN20 to TN22 to precharge the paired bit lines BLL, /BLL and equalize the potentials thereof. A precharge/equalizing circuit control signal xcfx86EQR is supplied to the gates of the MOS transistors TN23 to TN25 to precharge the paired bit lines BLR, /BLR and equalize the potentials thereof.
The bit switch 40 is constructed by N-channel MOS transistors TN40, TN41 and controlled by a bit switch control signal xcfx86L. The bit switch 41 is constructed by N-channel MOS transistors TN42, TN43 and controlled by a bit switch control signal xcfx86R.
In FIG. 1, an example in which the bit line /BLR is short-circuited to the word line WLR2 is shown and it is equivalently expressed by a resistor Rshort.
FIG. 2 is a block diagram showing an equalizing signal generation circuit 50 for generating a precharge/equalizing circuit control signal xcfx86EQL/R in the circuit shown in FIG. 1 based on an equalizing/precharge circuit control signal xcfx86EQLCONTL/R. FIG. 3 shows an example of the detail construction of the equalizing signal generation circuit 50. As shown in FIG. 3, the equalizing signal generation circuit 50 is constructed by cascade-connected inverters INV30, INV31, INV32. The equalizing/precharge circuit control signal xcfx86EQLCONTL/R is supplied to the input terminal of the inverter INV30 and the precharge/equalizing circuit control signal xcfx86EQL/R is output from the output terminal of the inverter INV 32.
FIG. 4 is a timing chart showing operation waveforms in a case where the word line WLL is selected in the circuit shown in FIG. 1. When an internal activation signal /ACTIVE is set to a low level, the equalizing/precharge circuit control signal xcfx86EQLCONTL/R of the paired bit lines BLL, /BLL on the selected side is set to a high level, the precharge/equalizing circuit control signal xcfx86EQL is set to a low level, and the bit line precharge circuit 20 is set into the OFF state. Further, the control signal xcfx86R of the bit switch 41 on the non-selected side is also set to the low level to electrically separate the paired bit lines BLR, /BLR on the non-selected side from the sense amplifiers 10, 11.
Next, the word line WLL is set to the high level potential, the cell transistor TN50 is set into the ON state, and data of the cell capacitor C10 is read out to the bit line BLL. After cell data is read out to the bit line BLL, the sense amplifier activation signal xcfx86SN is set to the low level and the sense amplifier activation signal xcfx86SP is set to the high level so that the N-channel and P-channel sense amplifiers 10, 11 can be activated to amplify the readout potential.
At this time, a case wherein the word line WLR1 and the bit line /BLR are short-circuited to each other via the short-circuit resistor is considered. At the non-selected time, the equalizing/precharge circuits 20, 21 are set in the ON state and all of the bit lines BLL, /BLL, BLR, /BLR are precharged to the VBL level. Therefore, even if the potential of the bit line /BLR is lowered by the leakage current, it is difficult to correctly effect the screening operation when the short-circuit resistance is relatively high. Particularly, in the shared sense amplifier system, since the bit line /BLR having the bit line leakage current is connected to the bit line /BLL which is adjacent to the bit line with the sense amplifiers 10, 11 disposed therebetween via the bit switches 40, 41, there occurs a possibility that the bit line precharge potential VBL is lowered. If the bit line precharge potential VBL is lowered, the readout margin is reduced when xe2x80x9c0xe2x80x9d data is read out from the memory cell.
However, at the non-selected time, since the potential VBL is generally supplied via the bit line precharge/equalizing circuits 20, 21 after passing through a current limiting element for suppressing an increase in the standby current, a lowering in the potential level due to the bit line leakage current will be compensated for to some extent. Therefore, it becomes more difficult to detect the defective bit line.
Further, the bit line leakage current causes the standby current of the semiconductor memory device to be increased and is an important factor for lowering the manufacturing yield. Particularly, in recent years, devices are extremely strongly required for lower power consumption as represented by portable information terminals and note-book type personal computers and it is strongly required to reduce the standby current.
Accordingly, an object of this invention is to provide a semiconductor memory device in which a bit line having a leakage current can be effectively screened.
Further, another object of this invention is to provide a semiconductor memory device in which an increase in the standby current due to a bit line leakage current can be suppressed.
Still another object of this invention is to provide a semiconductor memory device in which the manufacturing test yield can be improved and the number of defective products in the market after the shipment of the products can be suppressed.
The above object can be attained by a semiconductor memory device comprising a plurality of word lines; paired bit lines arranged to intersect the plurality of word lines; a plurality of memory cells connected to the plurality of word lines and paired bit lines; and a bit line precharge/equalizing circuit for precharging the paired bit lines and equalizing the potentials thereof; wherein the bit line precharge/equalizing circuit precharges the paired bit lines and equalizes the potentials thereof when an internal activation signal using an external signal as a trigger is set into a precharge state in a test mode, and after the delay of a preset period of time, the bit line precharge/equalizing circuit is set into an OFF state.
With the above construction, since the potentials of a bit line having the bit line leakage current and a bit line which is disposed adjacent to and on the opposite side of the bit line with the sense amplifier disposed therebetween are lowered from the precharge level to the ground level if the leakage current is caused by a short circuit between the bit line and the word line, it becomes possible to easily screen the bit line having the leakage current because the margin in the next readout cycle is reduced. Therefore, it is possible to detect the defective bit line at the test time in the wafer state and replace the defective portion by a redundancy circuit so as to improve the manufacturing yield and reduce the number of defective products in the market.
Further, the above object can be attained by a semiconductor memory device comprising a plurality of word lines; paired bit lines arranged to intersect the plurality of word lines; a plurality of memory cells connected to the plurality of word lines and paired bit lines; a bit line precharge potential generation circuit for generating a bit line precharge potential for precharging the paired bit lines and equalizing the potentials thereof; a bit line precharge/equalizing circuit for applying the bit line precharge potential generated from the bit line precharge potential generation circuit to the paired bit lines to precharge the paired bit lines and equalize the potentials thereof; and a current limiting element disposed between the bit line precharge potential generation circuit and the bit line precharge/equalizing circuit, for limiting the precharge current flowing in the paired bit lines; wherein the precharge current for the paired bit lines is controlled by increasing the conductance of the current limiting element at the active time and reducing the conductance of the current limiting element at the standby time.
With the above construction, the standby current is reduced by reducing the conductance of the current limiting element at the standby time and the sufficiently large operation margin can be attained by increasing the conductance of the current limiting element at the active time. Thus, the sufficiently large operation margin can be attained and an increase in the standby current due to the leakage current can be effectively reduced.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.